1. Field of the Invention
The present invention relates to a flat display and, more particularly, to a flat display permitting high-speed handling of display data validated immediately after an input of a frame start signal.
2. Description of the Related Art
In recent years, there has been a greater demand for a flat matrix display such as a plasma display (PDP), a liquid crystal display (LCD), or an elecroluminescent (EL) display because of its thin structure, or configuration, in contrast to a CRT. Requests for, especially, a color display are frequent these days.
Flat displays including a plasma display and an electroluminescent (EL) display are thin. Moreover, the flat displays also permit large display screens. The application range and production scale of the flat displays are therefore rapidly expanding.
In general, a flat display utilizes charges accumulated between electrodes and causes a discharge to emit light for display. For better understanding of the general principle of display, the structure and operation of, for example, a plasma display will be briefly described.
Well-known conventional plasma displays (AC type PDP) are a dual-electrode type that uses two electrodes for selective discharge (addressing discharge) and sustaining discharge and a triple-electrode type that uses three electrodes for addressing discharge.
In a plasma display (PDP) for a color display, ultraviolet rays resulting from discharges are used to excite phosphors formed in discharge cells. The phosphors are susceptible to the impact of ions or positive charges induced synchronously with discharge. The above dual-electrode type has a structure that the phosphors directly hit ions. This structure may reduce the service lives of phosphors.
To avoid the deterioration, the color plasma display usually employs the triple-electrode structure based on surface discharge.
The triple-electrode type uses an arrangement in which a third electrode is formed on the substrate on which first and second electrodes for sustaining discharge are arranged or an arrangement in which a third electrode is formed on another substrate opposed to the one on which first and second electrodes are arranged.
In the arrangement in which three electrodes are formed on the same substrate, the third electrode may be placed on or under the other two electrodes for sustaining discharge.
Furthermore, visible light emitted from phosphors may be transmitted or reflected by the phosphors for observation.
The foregoing plasma displays of different types have the same principle. Mention will therefore be made of a flat display in which first and second electrodes for sustaining discharge are formed on a first substrate and a third electrode is formed on a second substrate opposed to the first substrate, by presenting embodiments thereof.
FIG. 6(A) is a schematic plan view showing a configuration of the aforesaid triple-electrode type plasma display (PDP). FIG. 6(B) is a schematic sectional view of one of discharge cells 10 formed in the plasma display shown in FIG. 6(A).
As apparent from FIGS. 6(A) and 6(B), the plasma display comprises two glass substrates 12 and 13. The first substrate 13 has first electrodes (X electrodes) 14 and second electrodes (Y electrodes) 15. The first electrodes 14 and second electrodes 15 serve as sustaining electrodes, lie in parallel with one another, and are shielded with a dielectric layer 18.
A coat 21 made of magnesium oxide (MgO) is formed as a protective coat over the discharge surface that is the dielectric layer 18.
On the surface of the second substrate 12 opposed to the first glass substrate 13, electrodes 16 acting as third electrodes or address electrodes are formed to intersect the sustaining electrodes 14 and 15.
On the address electrodes 16, phosphors 19 each having one of red, green, and blue light-emitting characteristics are placed in discharge spaces 20 each defined by walls 17 formed on the surface of the second substrate 12 on which the address electrodes are arranged.
Discharge cells 10 in the plasma display are separated from one another by partitions.
In a plasma display 1 of the aforesaid example, the first electrodes (X electrodes) 14 and second electrodes (Y electrodes) 15 are lying in parallel with one another and are paired. The second electrodes (Y electrodes) 15 are driven independently, while the first electrodes (X electrodes) 14 act as a common electrode and are driven by a single driver.
FIG. 7 is a schematic block diagram showing peripheral circuits for driving the plasma display shown in FIGS. 6(A) and 6(B). The address electrodes 16 are connected one by one to an address driver 31. During addressing discharge, the address driver 31 applies an address pulse to each address electrode.
The Y electrodes 15 are connected one by one to an Y-electrode scan driver 34.
The scan driver 34 is connected to an Y-electrode common driver 33. For addressing discharge, pulses are generated by the scan driver 34. For sustaining discharge, pulses are generated by the Y-electrode common driver 33, and then applied to the Y electrodes 15 via the Y-electrode scan driver 34.
The X electrodes 14 are connected in common with respect to all display lines on a panel of the flat display.
An X-electrode common driver 32 generates a write pulse and a sustaining pulse, and applies these pulses to the Y electrodes 15 concurrently. These drivers are controlled by a control circuit. The control circuit is controlled with a synchronizing signal which is fed by an external unit.
As is apparent from FIG. 7, the address driver 31 is connected to a display data control unit 36 incorporated in the control circuit 35. The display data control unit 36 inputs a dot clock signal CLOCK and a display data signal DATA, which are display data and fed from an external unit, and outputs address data indicating address electrodes to be selected for each line with a horizontal synchronizing signal H.sub.SYNC.
The Y-electrode scan driver 34 is connected to a scan driver control unit 39 in a panel drive control unit 38 incorporated in the control circuit 35. In response to a vertical synchronizing signal V.sub.SYNC that is a signal instructing the start of scanning one frame and fed by an external unit, and a horizontal signal H.sub.SYNC that is a signal instructing the start of scanning one line, the Y-electrode scan driver 34 is driven to select a plurality of Y electrodes 15 in the flat display 1, one by one. Thus, an image of one frame is displayed.
In FIG. 7, Y-DATA denotes scan data that is supplied by the scan driver control unit 39 and used to turn on the Y-electrode scan driver bit by bit. Y-CLOCK denotes a transfer clock pulse for use in turning on the Y-electrode scan driver bit by bit.
Y-STB1 denotes a timing signal for use in turning on the Y-electrode scan driver. Y-STB2 denotes a timing signal for use in turning off the Y-electrode scan driver.
The X-electrode common driver 32 and Y-electrode common driver 33 in this example are connected to a common driver control unit 40 incorporated in the control circuit 35. The X electrodes 14 and Y electrodes 15 are driven all together by reversing polarities of applied voltages alternately. Thus, the aforesaid sustaining discharge is executed.
In FIG. 7, an X-UD signal is supplied by the common driver control unit 40, used to control the on and off states of the X common driver, and the X-UD signal includes voltage signals Vs and Vw. An X-DD signal supplied by the common driver control unit 40 is used to control the on and off states of the X-electrode common driver and the X-DD signal includes a GND level signal.
Likewise, a Y-UD signal supplied by the common driver control unit 40 is used to control the on and off states of the Y-electrode common driver, and the Y-UD signal includes voltage signals Vs and Vw. An Y-DD signal supplied by the common driver control unit 40 is used to control the on and off states of the Y-electrode common driver and the Y-DD signal includes a GND level signal.
Referring to the timing chart of FIG. 8, an example of an image display driving method will be described in conjunction with a conventional triple-electrode type plasma display (PDP) for color display with a single brightness level.
In a prior art, a line-sequential self-erasure addressing mode, in which signals are issued according to the timing shown in FIG. 8, has been adopted for driving.
According to this mode, a sustaining sequence including initialization of a display screen, writing of data, and displaying of data is performed during a pulse spacing of a signal H.sub.SYNC for defining a period of scanning one line Data writing is validated only for a selected line.
As apparent from FIG. 8, one H.sub.SYNC pulse spacing is segmented into a selected line writing period S1, a self-erasure addressing period S2, and a sustaining discharge period S3. Electric fields are induced from X electrodes associated with a selected line to Y electrodes associated therewith during the selected line writing period S1 in each H.sub.SYNC pulse spacing. Thus, sustaining discharge is carried out. Cells that were lit for a previous frame discharge during the sustaining discharge period, while cells that were not lit do not light. Sustaining discharge is performed again to induce larger electric fields from the X electrodes to the Y electrodes. Writing is then performed to light all the cells associated with the selected line. Thus, all the cells associated with the selected line light and hold internal electric fields resulting from wall charge therein. Consequently, a whole screen is initialized uniformly. Electric fields are then induced from the Y electrodes to X electrodes, whereby a sustaining discharge is effected to light all the cells.
During the self-erasure addressing period S2, the address electrodes associated with a selected line are supplied with address pulses. Display data are then written. This writing is accomplished by allowing the cells, which should not be displayed, to self-erase the internal electric fields.
In other words, a sustaining discharge achieved between X and Y electrodes, and generation of address pulses are stopped simultaneously so that the X and Y electrodes have the same voltage to eliminate external electric fields. When the address electrodes and Y electrodes are energized to induce inverse electric fields between them, self-erasure discharge occurs due to internal electric fields. Cells that are not written will not light during a succeeding sustaining discharge period S3.
Sustaining discharge is repeated between the X and Y electrodes until the line associated with the X and Y electrodes is selected for the next frame. Cells, which must be displayed, are kept lit. Cells, which should not be displayed, are not lit.
The aforesaid conventional mechanism of self-erasure in cells is based on internal electric fields in the cells. The magnitudes of the internal electric fields must therefore be determined somewhat precisely. A magnitude of an internal electric field in a cell or an amount of wall charge is greatly dependent on the state of the cell that is discharging to emit light. There are however difficulties in manufacturing a fully uniform display panel. The difficulties intensify with an increase in area of a display panel.
When initialization is executed to write data for one line, there is a difference in wall charge between cells that were lit for a previous frame and cells that were not lit. Moreover, some cells induce externally-applied electric fields whereas other cells induce internal electric fields. These facts pose a problem that self-erasure due to internal electric fields causes an erasure error of insufficient erasure and the erasure error triggers a write error. The write error eventually degrades the display quality.
To solve the above problem, the present applicant has proposed a driving method based on a batch writing/batch erasure/line-sequential addressing mode.
The driving method based on a batch writing/batch erasure/line-sequential addressing mode is shown schematically in FIG. 9 and will be described briefly.
In FIG. 9, one screen is displayed in units of one frame. In this driving method, driving is performed differently among an all-line batch writing/erasure period S1', an addressing period S2 during which all lines are scanned line by line and thus data are written line-sequentially, and a sustaining discharge period S3 during which a whole screen is displayed. This method is thought to enable stable addressing and writing.
Even in this method, a period during which batch writing and erasure is executed for all lines is required after a frame start control signal is sent until display data are written. When sufficient time is not ensured after a signal is sent from a host until data are transmitted, the method is inapplicable.
In the prior art, after a frame start control signal V.sub.SYNC is received, a time interval for initialization is required to ensure a period during which several pulses in a horizontal synchronizing signal H.sub.SYNC are input.
When a data signal for the first line follows immediately after the frame start control signal V.sub.SYNC, unless a frame memory or other data storage means is provided, data cannot be processed.
In the prior art, specification or standard designs are previously determined, and during a given period, corresponding to a period starting from the time when a given frame start control signal V.sub.SYNC is received to the time when several pulses of a horizontal synchronizing signals H.sub.SYNC are input, the input of a display data signal is disabled. A signal sent from a host cannot always be put to use.